🏗️ CPU Cache Topology - hello · Scour

On the Limits of Learned Importance Scoring for KV Cache Compression

arxiv.org·3h

⏪Deoptimization

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·12h

DiskCache: Disk Backed Cache — DiskCache 5.6.1 documentation

grantjenks.com·1d

💾Cache Design

CPU-bound Insert Benchmark vs MySQL on 24-core and 32-core servers

smalldatum.blogspot.com·1d·

Discuss: smalldatum.blogspot.com

🚀Performance

An Explosion In Interconnect Complexity

semiengineering.com·39m

⚡Circuit Design

Field Notes on Scaling MoE Expert Parallelism with DeepEP

nousresearch.com·1d·

Discuss: Lobsters, Hacker News

Phase-space engineering and collective dynamics in memcomputing

link.aps.org·1h

🎴SIMD Shuffles

I replaced my ChatGPT subscription with a 12GB GPU and never looked back

xda-developers.com·12h

A Quest to Find the Fastest Search Stack

dev.to·18h·

Discuss: DEV

🗄️Database Internals

Intel signals the end for its 12th Gen Core processors, though the architecture lives on under the guise of its 13th and 14th Gen

pcgamer.com

·1d

💻CPU Architecture

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

Syslogic offers cm-accurate expansion board for embedded computers

gpsworld.com·10h

🎛️Microcontrollers

Every Mini PC & SFF Hardware Announced at CES 2026

williamlam.com·17h

PI Introduces Miniaturized Alignment Engine Platform for Scalable, Parallel E/O Wafer-Level Test

prnewswire.com·19h

understanding LSM trees via read, write, and space amplification

bitsxpages.com·9h

Curbing Soaring Power Demand Through Foundation IP

semiwiki.com·18h

⚡Hardware Acceleration

Transmeta Crusoe CPU

dfarq.homeip.net·20h

🔄Hardware Transactional Memory

AMD's 3D V-Cache Is Such A Hit For L3 It May Stack L2 Cache On CPUs Next

hothardware.com·6d

🏗Computer Architecture

The new Ccleaner

forums.anandtech.com·13h

🗑️Garbage Collection

datahaven-xyz/datahaven: An EVM compatible Substrate chain, powered by StorageHub and secured by EigenLayer

github.com·6h

🎚️Tiered Storage

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